1. Field of the Invention
The present invention relates to a sense amplifier layout method of a semiconductor memory device, and in particular to a layout structure of NMOS transistors of a sense amplifier.
2. Description of the Background Art
A sense amplifier of a semiconductor memory device consists of a pull-up device using a PMOS transistor and a pull-down device using an NMOS transistor. The sense amplifier amplifies a data voltage applied to a bit line BL and a bit bar line /BL, and outputs the amplified voltage to a data bus.
FIG. 1 illustrates the sense amplifier of the semiconductor memory device. Referring to FIG. 1, the sense amplifier includes: a first sense amp unit 10 for sensing data of a bit bar line /BL0 and a bit line BL0; and a second sense amp unit 20 for sensing data of a bit bar line /BL1 and a bit line BL1. In the first sense amp unit 10, a PMOS transistor P1 and an NMOS transistor N1 are connected in series between a power supply voltage VDD and a ground VSS, and a PMOS transistor P2 and an NMOS transistor N2 are connected in series between the power supply voltage VDD and the ground VSS. The PMOS transistor P1 and the NMOS transistor N1 have their drains connected to the bit bar line /BL0 and their gates connected to the bit line BL0. In addition, the PMOS transistor P2 and the NMOS transistor N2 have their drains connected to the bit line BL0 and their gates connected to the bit bar line /BL0.
In the second sense amp unit 20, a PMOS transistor P3 and an NMOS transistor N3 are connected in series between the power supply voltage VDD and the ground VSS, and a PMOS transistor P4 and an NMOS transistor N4 are connected in series between the power supply voltage VDD and the ground VSS. The PMOS transistor P3 and the NMOS transistor N3 have their drains connected to the bit bar line /BL1 and their gates connected to the bit line BL1. In addition, the PMOS transistor P4 and the NMOS transistor N4 have their drains connected to the bit line BL1 and their gates connected to the bit bar line /BL1.
At an initial stage of the operation, the bit line BL0, the bit bar line /BL0, the bit line BL1 and the bit bar line /BL1 are precharged with half a power supply voltage xc2xd VDD, which is maintained as it is or slightly increased due to a voltage level of a data signal from a memory cell. A voltage increase ratio of the bit lines due to the voltage of the data signal is very small because of operation speed and size of the capacitor. Accordingly, the sense amplifier of the semiconductor memory device requires high sensitivity.
FIG. 2A is a layout diagram illustrating a conventional NMOS transistor unit of the first and second sense amp units 10, 20. As illustrated in FIG. 2A, the bit line BL0, the bit bar line /BL0, the bit line BL1 and the bit bar line /BL1 are formed in parallel in a longitudinal direction at predetermined intervals. The NMOS transistor (N1) 40 of the first sense amp unit 10 is formed at the upper portion of the bit line BL0 and the bit bar line /BL0, and the NMOS transistor (N2) 42 of the first sense amp unit 10 is formed at the lower portion thereof. The NMOS transistor (N4) 44 of the second sense amp unit 20 is formed at the upper portion of the bit line BL1 and the bit bar line /BL1, and the NMOS transistor (N3) 46 of the second sense amp unit 20 is formed at the lower portion thereof.
On the other hand, the ground line VSS is vertically formed at the left portion of the bit line BL0 in the NMOS transistor region 40 of the first sense amp unit 10, vertically formed at the right portion of the bit bar line /BL1 in the NMOS transistor region 44 of the second sense amp unit 20, and formed between the bit bar line /BL0 and the bit line BL1.
In the NMOS transistor region 40 of the first sense amp unit 10, a first gate contact G1 is formed on the bit line BL0, a first drain contact D1 is formed on the bit bar line /BL0, and a first source contact S1 is formed on the ground line VSS vertically formed at the left portion of the bit line BL0. In the NMOS transistor region 42 of the first sense amp unit 10, a second drain contact D2 is formed on the bit line BL0, a second gate contact G2 is formed on the bit bar line /BL0, and a second source contact S2 is formed on the ground line VSS vertically formed between the bit line BL0 and the bit bar line /BL0.
In the NMOS transistor region 44 of the second sense amp unit 20, a third drain contact D3 is formed on the bit line BL1, a third gate contact G3 is formed on the bit bar line /BL1, and a third source contact S3 is formed on the ground line VSS vertically formed at the right portion of the bit bar line /BL1. In the NMOS transistor region 46 of the second sense amp unit 20, a fourth gate contact G4 is formed on the bit line BL1, a fourth drain contact D4 is formed on the bit bar line /BL1, and a fourth source contact S4 is formed on the ground line VSS vertically formed between the bit line BL0 and the bit bar line /BL0.
FIG. 2B is a cross-sectional diagram taken along line IIxe2x80x94II of FIG. 2A. As shown in FIG. 2B, a p-type active region 52 is formed on a silicon wafer 51, and three n+ impurity regions 53, 54, 55 are formed in the active region 52. On the active region 52, a first gate 56 (electrode over gate insulator) is formed between the first impurity region 53 and the second impurity region 54, and a second gate 57 is formed between the second impurity region 54 and the third impurity region 55. An interlayer insulating film 58 is formed over the resultant structure having the first and second gates 56, 57. Contact holes (not shown) are formed to partially expose the first to third impurity regions 53, 54, 55. A conductive material formed over the resultant structure including the contact holes is partially patterned to form first to third conducting lines 59, 60, 61. The second drain contact D2 is formed between the conducting line 59 and the region 53. The second source contact S2 and the fourth source contact S4 are formed between the conducting line 60 and the region 54. And the fourth drain contact D4 is formed between the conducting line 61 and the region 55.
In the conventional sense amplifier layout method, as illustrated in FIG. 2A, the upper and lower portions of one bit line pitch L respectively have one NMOS transistor. Accordingly, one NMOS transistor is provided in one sense amp pitch L. As further shown in FIGS. 2A and 2B, the drain and source contacts of each NMOS transistor lie in a line (e.g., line IIxe2x80x94II) perpendicular to the longitudinal direction of the bit and bit bar lines. As extra material is needed when making a contact, the NMOS transistors extend beyond the sense amp pitch L, thereby increasing a layout area of the sense amplifier and decreasing a process margin. Moreover, a gate interconnection is used due to a deficient interconnection area, and thus the sense amplifier is influenced by a gate interconnection resistance, which reduces an operation speed or causes a mis-operation.
Therefore, it is an object of the present invention to provide a sense amplifier layout method of a semiconductor memory device which can decrease a layout area of a sense amplifier and increase a process margin.
Another object of the present invention is to provide a sense amplifier layout method of a semiconductor memory device which can increase an interconnection area, without requiring a gate interconnection.
In order to achieve the above-described objects of the present invention, there is provided an improved sense amplifier layout method of a semiconductor memory device. Firstly, a plurality of bit lines and bit bar lines are alternately aligned in parallel. One bit line and one bit bar line form a bit line pair. Only one MOS transistor for configuring a sense amplifier is disposed over a predetermined number of bit line pairs in the width direction, and a predetermined number of the MOS transistors are disposed over the bit line pairs in the longitudinal direction. The gates of the MOS transistors are formed over at least a portion of the plurality of bit line pairs in the width direction. Preferably, the gates of the MOS transistors are formed in a ring or rectangle shape.
Especially, the MOS transistors are extended over the two bit line pairs. The two bit line pairs include a first bit line, a first bit bar line, a second bit line and a second bit bar line. The first to fourth MOS transistors are aligned on the two bit line pairs in the longitudinal direction. The first and second MOS transistors compose one cross-coupled MOS, and the third and fourth MOS transistors compose the other cross-coupled MOS.
In the first MOS transistor, a first gate contact is formed on the first bit line, a first drain contact is formed on the first bit bar line, and a first source contact is formed on a ground line formed between the first bit line and the first bit bar line. In the second MOS transistor, a second drain contact is formed on the first bit line, a second gate contact is formed on the first bit bar line, and a second source contact is formed on the ground line formed between the first bit line and the first bit bar line. In the third MOS transistor, a third gate contact is formed on the second bit line, a third drain contact is formed on the second bit bar line, and a third source contact is formed on a ground line formed between the second bit line and the second bit bar line. In the fourth MOS transistor, a fourth drain contact is formed on the second bit line, a fourth gate contact is formed on the second bit bar line, and a fourth source contact is formed on the ground line formed between the second bit line and the second bit bar line.
According to the above-mentioned configuration, only one NMOS transistor is arranged on two bit line pitches (2L), thereby reducing a layout area of the sense amplifier and increasing a process margin. In addition, an interconnection area is increased by aligning one NMOS transistor at the upper and lower portions of the two bit line pitches (2L), and thus a gate interconnection is not required. It is therefore possible to improve an unstable operation of the sense amplifier resulting from a gate interconnection resistance.